The present invention relates to a method of forming micro patterns of a semiconductor device and, more particularly, to a method of forming micro patterns in which target patterns arranged in matrix form are created with features (e.g., pitch) smaller than the resolution of an exposure apparatus.
A plurality of semiconductor elements, such as a transistor and metal lines for electrically connecting the semiconductor elements, are formed in a semiconductor substrate. The metal lines and a junction region (e.g., the source or drain of the transistor) of the semiconductor substrate are electrically connected by a contact plug.
In the case of DRAM devices, a transistor and a storage node contact plug are formed in a semiconductor substrate. To this end, an interlayer dielectric layer and contact holes are first formed. DRAM is classified into various types according to the arrangement of the memory cell arrays. In 6F2 DRAM devices, active regions are arranged in matrix form in a cell region. In particular, the active regions are formed in a rectangular form with regular spacing. As the degree of integration increases, the size or spacing of the active regions in the 6F2 DRAM device can have a pitch smaller than the resolution limit of an exposure apparatus. Due to this, when forming a photoresist pattern for defining the active regions, an exposure process on a photoresist film may have to be performed more than once. Consequently, the process cost increases and it is also difficult to reduce k1 (i.e., the scale of the resolution) to 0.20 or less.